Digital Eletronics – Perform spectral analysis on the audio signals, Singapore

Assignment Details:

1. In this Problem you are to perform spectral analysis on the audio signals You are given a short piano piece “piano_sequence.wav” of duration 3 measures. The second musical note and first chord (combination of notes) are given separately in “piano_single_note.wav” and “piano_chord.wav” respectively.

Write a MATLAB program to perform the followings:

1. Read “piano_single_note.wav” into a vector
2. Determine the sampling rate and number of samples in
3. Use MATLAB built-in function to perform DFT on x, and save the result in
4. Create an array freq (in Hz) that represents the actual frequencies corresponding to the indices of
5. Plot the |X(f)| vs freq from 0Hz to 3kHz.
6. From the spectrum, determine the fundamental frequency and its harmonics of the single
7. Repeat the same spectra analysis for “piano_chord.wav”, including plotting

|X(f)| vs freq.

1. From the spectrum of “piano_chord”, group the fundamental frequency and it harmonics that belong to the same musical Determine the fundamental frequency of each note.

2. Exporting your filter designs in 4(a) and 4(b) to

In SIMULINK, create two discrete-time signals x₁[n], x₂[n] supposition with a band limited white noise as follow:

T_c = 0.000021 sec

noise power: 0.0000021

x₁[n] = sin(2nf₁nT_c) + noise,        f₁ = 3kHz x₂[n] = sin(2nf₂nT_c) + noise,     f₂ = 12kHz

Submit the circuit diagrams that show the connections of the discretised signal source, band limited white noise source, digital filters, and the scope capturing the input and output signals.

Plot the input and output signals in the time-domain before and after the filters, for all 4 cases (2 signals x 2 filters). From the filter design frequency response, estimate the attenuation expect at 3kHz and 12kHz.

Comment on the waveforms.

3. Write a VHDL code to implement the circuit function described

The circuit is to display the last four digits of your student ID number on a 7-segment display, one digit at a time, triggered by the falling edge of the clock signal.

DIR: Direction of the display sequence, ‘1’ = forward, ‘0’ = reverse. CLK: clock pulse for the display sequence.

RST: reset the display counter.

ID number is 3313, the last four digits are ‘3’, ‘3’, ‘1’, ‘3’, and the circuit is to display ‘3’, ‘3’, ‘1’, ‘3’,’3’, ‘3’,’1’,’3’…when DIR = ‘1’ and display

‘3’,’3’,’1’,’3’,’3’,’3’,’1’,’3’,’3’…when DIR = ‘0’.

Code must be well-organized and clearly explained.

Write a small test bench code to perform the simulation and verification.

Submit your VHDL code, test bench code and the simulation waveforms.